In a semiconductor device assembly, an integrated circuit die (also referred to as a semiconductor chip or “die”) may be mounted on a semiconductor substrate. Driven by the demand for high performance and lower costs, integrated circuit packages have begun to incorporate multiple die in a single package. However, such integration constitutes a significant challenge in creating reliable stacking structures that can support continuous device scaling and higher operating speed for future generations of integrated circuit devices.
Generally, interconnection structures such as embedded silicon bridges are typically provided at package substrate level to enable high-density die-to-die connection in integrated circuit packages. The use of an embedded silicon bridge eliminates the need for through-silicon vias (TSVs) and interposer structures. However, the process of embedding the silicon bridge may result in a high yield loss. The embedded nature of the silicon bridge may also complicate microbump assembly involving the package substrate and die-to-die connection testing after assembly. Additionally, the implementation of the embedded silicon bridge may necessitate the consumption of an expensive substrate before knowing if the die-to-die connection is good, thereby increasing fabrication costs wasted on bad assemblies.